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max_uart_vhdl
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9 Commits (6c1005a6af8766175ba86cb3e78db10aa3d088d9)
 

Author SHA1 Message Date
Maximilian Stiefel 6c1005a6af Renamed all VHDL files
5 years ago
Maximilian Stiefel ef83326ee0 Quick fix concerning bit order
5 years ago
Maximilian Stiefel 582bdcde68 Added .pcf file
5 years ago
Maximilian Stiefel 5c8671e7e3 Top design for UART hello_world seems to work
5 years ago
Maximilian Stiefel d62bfceea0 Introducing the string sender
5 years ago
Maximilian Stiefel 2c415fd7c7 Clock divider seems to work. Further testing needed
5 years ago
Maximilian Stiefel 885e45b3c2 UART TX module works.
5 years ago
Maximilian Stiefel 41d09c015e Got simple example working with gtkwave
5 years ago
Maximilian Stiefel b0f5a9dea9 Initial commit
5 years ago