4 changed files with 90 additions and 0 deletions
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*.swp |
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*.vcd |
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*.cf |
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entity adder is |
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-- i0, i1 and the carry-in ci are inputs of the adder. |
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-- s is the sum output, co is the carry-out. |
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port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit); |
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end adder; |
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|
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architecture rtl of adder is |
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begin |
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-- This full-adder architecture contains two concurrent assignment. |
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-- Compute the sum. |
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s <= i0 xor i1 xor ci; |
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-- Compute the carry. |
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co <= (i0 and i1) or (i0 and ci) or (i1 and ci); |
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end rtl; |
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-- A testbench has no ports. |
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entity adder_tb is |
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end adder_tb; |
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|
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architecture behav of adder_tb is |
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-- Declaration of the component that will be instantiated. |
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component adder |
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port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit); |
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end component; |
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-- Specifies which entity is bound with the component. |
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for adder_0: adder use entity work.adder; |
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signal i0, i1, ci, s, co : bit; |
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begin |
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-- Component instantiation. |
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adder_0: adder port map (i0 => i0, i1 => i1, ci => ci, |
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s => s, co => co); |
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|
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-- This process does the real job. |
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process |
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type pattern_type is record |
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-- The inputs of the adder. |
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i0, i1, ci : bit; |
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-- The expected outputs of the adder. |
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s, co : bit; |
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end record; |
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-- The patterns to apply. |
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type pattern_array is array (natural range <>) of pattern_type; |
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constant patterns : pattern_array := |
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(('0', '0', '0', '0', '0'), |
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('0', '0', '1', '1', '0'), |
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('0', '1', '0', '1', '0'), |
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('0', '1', '1', '0', '1'), |
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('1', '0', '0', '1', '0'), |
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('1', '0', '1', '0', '1'), |
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('1', '1', '0', '0', '1'), |
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('1', '1', '1', '1', '1')); |
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begin |
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-- Check each pattern. |
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for i in patterns'range loop |
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-- Set the inputs. |
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i0 <= patterns(i).i0; |
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i1 <= patterns(i).i1; |
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ci <= patterns(i).ci; |
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-- Wait for the results. |
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wait for 1 ns; |
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-- Check the outputs. |
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assert s = patterns(i).s |
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report "bad sum value" severity error; |
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assert co = patterns(i).co |
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report "bad carray out value" severity error; |
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end loop; |
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assert false report "end of test" severity note; |
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-- Wait forever; this will finish the simulation. |
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wait; |
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end process; |
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end behav; |
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-- Hello world program. |
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use std.textio.all; -- Imports the standard textio package. |
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|
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-- Defines a design entity, without any ports. |
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entity hello_world is |
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end hello_world; |
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|
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architecture behaviour of hello_world is |
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begin |
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process |
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variable l : line; |
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begin |
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write (l, String'("Hello world!")); |
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writeline (output, l); |
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wait; |
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end process; |
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end behaviour; |
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