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14 lines
434 B
14 lines
434 B
entity adder is
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-- i0, i1 and the carry-in ci are inputs of the adder.
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-- s is the sum output, co is the carry-out.
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port (i0, i1 : in bit; ci : in bit; s : out bit; co : out bit);
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end adder;
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architecture rtl of adder is
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begin
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-- This full-adder architecture contains two concurrent assignment.
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-- Compute the sum.
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s <= i0 xor i1 xor ci;
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-- Compute the carry.
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co <= (i0 and i1) or (i0 and ci) or (i1 and ci);
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end rtl;
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