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@ -15,6 +15,7 @@ architecture uart_tx_tb_rtl of uart_tx_tb is |
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i_clk_baudrate : in std_logic; |
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i_clk_baudrate : in std_logic; |
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i_reset_n : in std_logic; |
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i_reset_n : in std_logic; |
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i_tx_send : in std_logic; |
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i_tx_send : in std_logic; |
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i_msb_first : in std_logic; |
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i_tx_data_vec : in std_logic_vector(7 downto 0); |
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i_tx_data_vec : in std_logic_vector(7 downto 0); |
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o_tx_pin : out std_logic; |
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o_tx_pin : out std_logic; |
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o_tx_sent : out std_logic |
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o_tx_sent : out std_logic |
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@ -26,6 +27,7 @@ architecture uart_tx_tb_rtl of uart_tx_tb is |
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signal tb_i_clk_baudrate : std_logic := '0'; |
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signal tb_i_clk_baudrate : std_logic := '0'; |
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signal tb_i_reset_n : std_logic := '0'; |
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signal tb_i_reset_n : std_logic := '0'; |
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signal tb_i_tx_send : std_logic := '0'; |
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signal tb_i_tx_send : std_logic := '0'; |
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signal tb_i_msb_first : std_logic := '0'; |
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signal tb_i_tx_data_vec : std_logic_vector(7 downto 0) := x"00"; |
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signal tb_i_tx_data_vec : std_logic_vector(7 downto 0) := x"00"; |
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signal tb_o_tx_pin : std_logic := '0'; |
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signal tb_o_tx_pin : std_logic := '0'; |
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signal tb_o_tx_sent : std_logic := '0'; |
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signal tb_o_tx_sent : std_logic := '0'; |
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@ -36,6 +38,7 @@ begin |
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i_clk_baudrate => tb_i_clk_baudrate, |
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i_clk_baudrate => tb_i_clk_baudrate, |
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i_reset_n => tb_i_reset_n, |
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i_reset_n => tb_i_reset_n, |
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i_tx_send => tb_i_tx_send, |
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i_tx_send => tb_i_tx_send, |
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i_msb_first => tb_i_msb_first, |
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i_tx_data_vec => tb_i_tx_data_vec, |
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i_tx_data_vec => tb_i_tx_data_vec, |
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o_tx_pin => tb_o_tx_pin, |
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o_tx_pin => tb_o_tx_pin, |
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o_tx_sent => tb_o_tx_sent |
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o_tx_sent => tb_o_tx_sent |
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@ -64,6 +67,7 @@ begin |
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for sanny in nice_words'range loop |
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for sanny in nice_words'range loop |
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-- Feed with data and tell transmitter to send. |
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-- Feed with data and tell transmitter to send. |
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tb_i_tx_data_vec <= nice_words(sanny); |
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tb_i_tx_data_vec <= nice_words(sanny); |
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tb_i_msb_first <= not tb_i_msb_first; |
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tb_i_tx_send <= '1'; |
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tb_i_tx_send <= '1'; |
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-- Wait until transmitted then finish simulation. |
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-- Wait until transmitted then finish simulation. |
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wait until tb_o_tx_sent = '1'; |
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wait until tb_o_tx_sent = '1'; |
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