Created a so far simple package file

uart.vhd

@@ -0,0 +1,16 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+package uart_pkg is
+  component uart_tx is
+    port(
+          i_clk_baudrate  : in  std_logic;
+          i_reset_n       : in  std_logic;
+          i_tx_send       : in  std_logic;
+          i_tx_data_vec   : in  std_logic_vector(7 downto 0);
+          o_tx_pin        : out std_logic;
+          o_tx_sent       : out std_logic
+        );
+  end component;
+end package;