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82 lines
2.9 KiB
82 lines
2.9 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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-- Testbenches do not have ports.
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entity uart_tx_tb is
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end uart_tx_tb;
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architecture uart_tx_tb_rtl of uart_tx_tb is
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-- 10 MHz clock
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constant c_CLK_PERIOD : time := 100 ns;
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--Declaration of component we will instantiate.
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component uart_tx
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port (
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i_clk_baudrate : in std_logic;
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i_reset_n : in std_logic;
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i_tx_send : in std_logic;
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i_msb_first : in std_logic;
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i_tx_data_vec : in std_logic_vector(7 downto 0);
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o_tx_pin : out std_logic;
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o_tx_sent : out std_logic
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);
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end component;
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-- Which entity is bound with the component.
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for uart_tx_0: uart_tx use entity work.uart_tx;
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-- Signals for test stimuli.
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signal tb_i_clk_baudrate : std_logic := '0';
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signal tb_i_reset_n : std_logic := '0';
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signal tb_i_tx_send : std_logic := '0';
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signal tb_i_msb_first : std_logic := '0';
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signal tb_i_tx_data_vec : std_logic_vector(7 downto 0) := x"00";
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signal tb_o_tx_pin : std_logic := '0';
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signal tb_o_tx_sent : std_logic := '0';
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signal tb_done : std_logic := '0';
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begin
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-- Instatiating component.
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uart_tx_0: uart_tx port map (
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i_clk_baudrate => tb_i_clk_baudrate,
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i_reset_n => tb_i_reset_n,
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i_tx_send => tb_i_tx_send,
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i_msb_first => tb_i_msb_first,
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i_tx_data_vec => tb_i_tx_data_vec,
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o_tx_pin => tb_o_tx_pin,
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o_tx_sent => tb_o_tx_sent
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);
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-- Generate clock.
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p_clock : process is
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begin
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if (tb_done = '0') then
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tb_i_clk_baudrate <= '0';
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wait for c_CLK_PERIOD/2;
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tb_i_clk_baudrate <= '1';
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wait for c_CLK_PERIOD/2;
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elsif tb_done = '1' then
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wait;
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end if;
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end process p_clock;
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-- Generate further testing stimuli in addition.
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p_stimuli : process is
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type vector_array_t is array (0 to 3) of std_logic_vector(7 downto 0);
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constant nice_words : vector_array_t := (x"BE", x"EF", x"BA", x"BE");
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begin
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-- Reset transmitter.
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tb_i_reset_n <= '0';
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wait for c_CLK_PERIOD;
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tb_i_reset_n <= '1';
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for sanny in nice_words'range loop
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-- Feed with data and tell transmitter to send.
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tb_i_tx_data_vec <= nice_words(sanny);
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tb_i_msb_first <= not tb_i_msb_first;
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tb_i_tx_send <= '1';
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-- Wait until transmitted then finish simulation.
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wait until tb_o_tx_sent = '1';
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tb_i_tx_send <= '0';
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wait for c_CLK_PERIOD*1.5;
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end loop;
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tb_done <= '1';
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assert false report "end of test" severity note;
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wait;
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-- Wait forever, which will finish the simulation.
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end process p_stimuli;
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end uart_tx_tb_rtl;
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