library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

-- Testbenches do not have ports.
entity uart_tx_tb is
end uart_tx_tb;

architecture uart_tx_tb_rtl of uart_tx_tb is
  -- 10 MHz clock
  constant c_CLK_PERIOD : time := 100 ns;
  --Declaration of component we will instantiate.
  component uart_tx
    port (
          i_clk_baudrate  : in  std_logic;
          i_reset_n       : in  std_logic;
          i_tx_send       : in  std_logic;
          i_msb_first     : in  std_logic;
          i_tx_data_vec   : in  std_logic_vector(7 downto 0);
          o_tx_pin        : out std_logic;
          o_tx_sent       : out std_logic
         );
  end component;
  -- Which entity is bound with the component.
  for uart_tx_0: uart_tx use entity work.uart_tx;
  -- Signals for test stimuli.
  signal tb_i_clk_baudrate  : std_logic := '0';
  signal tb_i_reset_n       : std_logic := '0';
  signal tb_i_tx_send       : std_logic := '0';
  signal tb_i_msb_first     : std_logic := '0';
  signal tb_i_tx_data_vec   : std_logic_vector(7 downto 0) := x"00";
  signal tb_o_tx_pin        : std_logic := '0';
  signal tb_o_tx_sent       : std_logic := '0';
  signal tb_done            : std_logic := '0';
begin
  -- Instatiating component.
  uart_tx_0: uart_tx port map (
                                i_clk_baudrate  => tb_i_clk_baudrate,
                                i_reset_n       => tb_i_reset_n,
                                i_tx_send       => tb_i_tx_send,
                                i_msb_first     => tb_i_msb_first,
                                i_tx_data_vec   => tb_i_tx_data_vec,
                                o_tx_pin        => tb_o_tx_pin,
                                o_tx_sent       => tb_o_tx_sent
                              );
  -- Generate clock.
  p_clock : process is
  begin
    if (tb_done = '0') then
      tb_i_clk_baudrate <= '0';
      wait for c_CLK_PERIOD/2;
      tb_i_clk_baudrate <= '1';
      wait for c_CLK_PERIOD/2;
    elsif tb_done = '1' then
      wait;
    end if;
  end process p_clock;
  -- Generate further testing stimuli in addition.
  p_stimuli : process is
    type vector_array_t is array (0 to 3) of std_logic_vector(7 downto 0);
    constant nice_words : vector_array_t := (x"BE", x"EF", x"BA", x"BE");
  begin
    -- Reset transmitter.
    tb_i_reset_n <= '0';
    wait for c_CLK_PERIOD;
    tb_i_reset_n <= '1';
    for sanny in nice_words'range loop
      -- Feed with data and tell transmitter to send.
      tb_i_tx_data_vec <= nice_words(sanny);
      tb_i_msb_first <= not tb_i_msb_first;
      tb_i_tx_send <= '1';
      -- Wait until transmitted then finish simulation.
      wait until tb_o_tx_sent = '1';
      tb_i_tx_send <= '0';
      wait for c_CLK_PERIOD*1.5;
    end loop;
    tb_done <= '1';
    assert false report "end of test" severity note;
    wait;
  -- Wait forever, which will finish the simulation.
  end process p_stimuli;
end uart_tx_tb_rtl;