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48 lines
1.1 KiB
48 lines
1.1 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity top_tb is
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end top_tb;
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architecture top_tb_rtl of top_tb is
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constant c_CLK_PERIOD : time := 83.33 ns;
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signal tb_clk_12mhz : std_logic := '0';
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signal tb_reset_n : std_logic := '1';
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signal tb_tx_pin : std_logic := '1';
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signal tb_led : std_logic := '0';
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signal tb_done : std_logic := '0';
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begin
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top_0: entity work.top(top_rtl)
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port map(
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i_clk_12mhz => tb_clk_12mhz,
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i_reset_n => tb_reset_n,
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o_tx_pin => tb_tx_pin,
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o_led => tb_led
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);
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-- Generate clock.
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p_clock : process is
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begin
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if (tb_done = '0') then
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tb_clk_12mhz <= '0';
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wait for c_CLK_PERIOD/2;
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tb_clk_12mhz <= '1';
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wait for c_CLK_PERIOD/2;
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elsif tb_done = '1' then
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wait;
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end if;
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end process p_clock;
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-- Process for stimuli.
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p_stimuli : process is
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begin
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tb_reset_n <= '0';
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wait for 2*c_CLK_PERIOD;
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tb_reset_n <= '1';
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wait for 1100 ms;
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tb_done <= '1';
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assert false report "end of test" severity note;
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wait;
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end process p_stimuli;
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end;
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