library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top_tb is
end top_tb;

architecture top_tb_rtl of top_tb is
  constant c_CLK_PERIOD : time    := 83.33 ns;

  signal tb_clk_12mhz : std_logic := '0';
  signal tb_reset_n   : std_logic := '1';
  signal tb_tx_pin    : std_logic := '1';
  signal tb_led       : std_logic := '0';
  signal tb_done      : std_logic := '0';

begin
  top_0: entity work.top(top_rtl)
  port map(
            i_clk_12mhz   => tb_clk_12mhz,
            i_reset_n     => tb_reset_n,
            o_tx_pin      => tb_tx_pin,
            o_led         => tb_led
          );
  -- Generate clock.
  p_clock : process is
  begin
    if (tb_done = '0') then
      tb_clk_12mhz <= '0';
      wait for c_CLK_PERIOD/2;
      tb_clk_12mhz <= '1';
      wait for c_CLK_PERIOD/2;
    elsif tb_done = '1' then
      wait;
    end if;
  end process p_clock;
  -- Process for stimuli.
  p_stimuli : process is
  begin
    tb_reset_n <= '0';
    wait for 2*c_CLK_PERIOD;
    tb_reset_n <= '1';
    wait for 1100 ms;
    tb_done <= '1';
    assert false report "end of test" severity note;
    wait;
  end process p_stimuli;
end;