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73 lines
2.4 KiB
73 lines
2.4 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity top is
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port (
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i_clk_12mhz : in std_logic;
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i_reset_n : in std_logic;
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o_tx_pin : out std_logic;
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-- o_dcd_n : out std_logic;
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-- o_dsr_n : out std_logic;
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-- o_cts_n : out std_logic;
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o_led : out std_logic
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);
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end top;
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architecture top_rtl of top is
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constant c_N_0 : integer := 30;
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constant c_divisor_0 : integer := 12e6;
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constant c_divisor_1 : integer := 1250;
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constant s_divisor_vec_0 : std_logic_vector(c_N_0-1 downto 0)
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:= std_logic_vector(to_unsigned(c_divisor_0, c_N_0));
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constant s_divisor_vec_1 : std_logic_vector(c_N_0-1 downto 0)
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:= std_logic_vector(to_unsigned(c_divisor_1, c_N_0));
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signal s_send_clk : std_logic := '0';
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signal s_sent : std_logic := '1';
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signal s_send : std_logic := '1';
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signal s_char_vec : std_logic_vector(7 downto 0) := (others => '0');
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signal s_baudrate_clk : std_logic := '0';
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begin
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-- Clock divider 0 gives the signal for when to send the string
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clock_divider_0: entity work.clock_divider(clock_divider_rtl)
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generic map (N => c_N_0)
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port map (
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i_clk => i_clk_12mhz,
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i_reset_n => i_reset_n,
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i_divisor_vec => s_divisor_vec_0,
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o_clk => s_send_clk
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);
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-- Clock divider 1 produces a baudrate of 9600 Bd
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clock_divider_1: entity work.clock_divider(clock_divider_rtl)
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generic map (N => c_N_0)
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port map (
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i_clk => i_clk_12mhz,
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i_reset_n => i_reset_n,
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i_divisor_vec => s_divisor_vec_1,
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o_clk => s_baudrate_clk
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);
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-- String sender component
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string_send_0: entity work.string_sender(string_sender_rtl)
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port map (
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i_clk => i_clk_12mhz,
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i_send_clk => s_send_clk,
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i_sent => s_sent,
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i_reset_n => i_reset_n,
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o_send => s_send,
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o_char => s_char_vec
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);
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-- UART transmitter component
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uart_tx_0: entity work.uart_tx(uart_tx_rtl)
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port map (
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i_clk_baudrate => s_baudrate_clk,
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i_reset_n => i_reset_n,
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i_tx_send => s_send,
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i_tx_data_vec => s_char_vec,
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o_tx_pin => o_tx_pin,
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o_tx_sent => s_sent
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);
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-- Couple send signal with LED
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o_led <= not s_send;
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end;
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