library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity top is
  port (
        i_clk_12mhz : in std_logic;
        i_reset_n   : in std_logic;
        o_tx_pin    : out std_logic;
--        o_dcd_n     : out std_logic;
--        o_dsr_n     : out std_logic;
--        o_cts_n     : out std_logic;
        o_led       : out std_logic
       );
end top;

architecture top_rtl of top is
  constant c_N_0          : integer := 30;
  constant c_divisor_0    : integer := 12e6;
  constant c_divisor_1    : integer := 1250;
  constant s_divisor_vec_0  : std_logic_vector(c_N_0-1 downto 0)
    := std_logic_vector(to_unsigned(c_divisor_0, c_N_0));
  constant s_divisor_vec_1  : std_logic_vector(c_N_0-1 downto 0)
    := std_logic_vector(to_unsigned(c_divisor_1, c_N_0));

  signal s_send_clk       : std_logic := '0';
  signal s_sent           : std_logic := '1';
  signal s_send           : std_logic := '1';
  signal s_char_vec       : std_logic_vector(7 downto 0) := (others => '0');
  signal s_baudrate_clk   : std_logic := '0';

begin
  -- Clock divider 0 gives the signal for when to send the string
  clock_divider_0: entity work.clock_divider(clock_divider_rtl)
  generic map (N => c_N_0)
  port map (
             i_clk => i_clk_12mhz,
             i_reset_n => i_reset_n,
             i_divisor_vec => s_divisor_vec_0,
             o_clk => s_send_clk
           );
  -- Clock divider 1 produces a baudrate of 9600 Bd
  clock_divider_1: entity work.clock_divider(clock_divider_rtl)
  generic map (N => c_N_0)
  port map (
             i_clk => i_clk_12mhz,
             i_reset_n => i_reset_n,
             i_divisor_vec => s_divisor_vec_1,
             o_clk => s_baudrate_clk
           );
  -- String sender component
  string_send_0: entity work.string_sender(string_sender_rtl)
  port map (
          i_clk => i_clk_12mhz,
          i_send_clk => s_send_clk,
          i_sent => s_sent,
          i_reset_n => i_reset_n,
          o_send => s_send,
          o_char => s_char_vec
         );
  -- UART transmitter component
  uart_tx_0: entity work.uart_tx(uart_tx_rtl)
  port map  (
              i_clk_baudrate  => s_baudrate_clk,
              i_reset_n       => i_reset_n,
              i_tx_send       => s_send,
              i_tx_data_vec   => s_char_vec,
              o_tx_pin        => o_tx_pin,
              o_tx_sent       => s_sent
            );
  -- Couple send signal with LED
  o_led <= not s_send;
end;