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100 lines
2.5 KiB
100 lines
2.5 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity string_sender_tb is
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end string_sender_tb;
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architecture string_sender_tb_rtl of string_sender_tb is
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-- 10 MHz clock
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constant c_CLK_PERIOD : time := 100 ns;
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signal tb_i_clk : std_logic := '0';
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signal tb_i_send_clk : std_logic := '0';
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signal tb_i_sent : std_logic := '1';
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signal tb_i_reset_n : std_logic := '1';
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signal tb_o_send : std_logic := '0';
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signal tb_o_char : std_logic_vector(7 downto 0) := (others => '0');
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signal tb_done : std_logic := '0';
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begin
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string_send_0: entity work.string_sender(string_sender_rtl)
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port map (
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i_clk => tb_i_clk,
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i_send_clk => tb_i_send_clk,
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i_sent => tb_i_sent,
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i_reset_n => tb_i_reset_n,
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o_send => tb_o_send,
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o_char => tb_o_char
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);
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-- Generate clock.
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p_clock : process is
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begin
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if (tb_done = '0') then
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tb_i_clk <= '0';
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wait for c_CLK_PERIOD/2;
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tb_i_clk <= '1';
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wait for c_CLK_PERIOD/2;
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elsif tb_done = '1' then
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wait;
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end if;
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end process p_clock;
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-- Generate send clock.
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p_sclock : process is
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begin
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if (tb_done = '0') then
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tb_i_send_clk <= '0';
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wait for 100 us;
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tb_i_send_clk <= '1';
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wait for 100 us;
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elsif tb_done = '1' then
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wait;
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end if;
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end process p_sclock;
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-- Process for stimuli.
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p_stimuli : process is
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begin
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tb_i_reset_n <= '0';
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wait for 2*c_CLK_PERIOD;
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tb_i_reset_n <= '1';
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wait for 1 ms;
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tb_done <= '1';
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assert false report "end of test" severity note;
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wait;
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end process p_stimuli;
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p_ssp: process(tb_i_clk)
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type z_ssp_t is (
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idle,
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busy,
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sending
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);
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variable v_cnt : integer range 0 to 20 := 0;
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variable z_ssp : z_ssp_t := idle;
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begin
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if rising_edge(tb_i_clk) then
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case z_ssp is
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when idle =>
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if tb_o_send = '1' then
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v_cnt := 0;
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tb_i_sent <= '1';
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z_ssp := busy;
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end if;
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when busy =>
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if v_cnt = 10 then
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v_cnt := 0;
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tb_i_sent <= '0';
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z_ssp := sending;
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else
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v_cnt := v_cnt + 1;
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end if;
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when sending =>
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if v_cnt = 20 then
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v_cnt := 0;
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tb_i_sent <= '1';
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z_ssp := idle;
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else
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v_cnt := v_cnt + 1;
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end if;
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end case;
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end if;
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end process p_ssp;
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end;
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