library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity string_sender_tb is end string_sender_tb; architecture string_sender_tb_rtl of string_sender_tb is -- 10 MHz clock constant c_CLK_PERIOD : time := 100 ns; signal tb_i_clk : std_logic := '0'; signal tb_i_send_clk : std_logic := '0'; signal tb_i_sent : std_logic := '1'; signal tb_i_reset_n : std_logic := '1'; signal tb_o_send : std_logic := '0'; signal tb_o_char : std_logic_vector(7 downto 0) := (others => '0'); signal tb_done : std_logic := '0'; begin string_send_0: entity work.string_sender(string_sender_rtl) port map ( i_clk => tb_i_clk, i_send_clk => tb_i_send_clk, i_sent => tb_i_sent, i_reset_n => tb_i_reset_n, o_send => tb_o_send, o_char => tb_o_char ); -- Generate clock. p_clock : process is begin if (tb_done = '0') then tb_i_clk <= '0'; wait for c_CLK_PERIOD/2; tb_i_clk <= '1'; wait for c_CLK_PERIOD/2; elsif tb_done = '1' then wait; end if; end process p_clock; -- Generate send clock. p_sclock : process is begin if (tb_done = '0') then tb_i_send_clk <= '0'; wait for 100 us; tb_i_send_clk <= '1'; wait for 100 us; elsif tb_done = '1' then wait; end if; end process p_sclock; -- Process for stimuli. p_stimuli : process is begin tb_i_reset_n <= '0'; wait for 2*c_CLK_PERIOD; tb_i_reset_n <= '1'; wait for 1 ms; tb_done <= '1'; assert false report "end of test" severity note; wait; end process p_stimuli; p_ssp: process(tb_i_clk) type z_ssp_t is ( idle, busy, sending ); variable v_cnt : integer range 0 to 20 := 0; variable z_ssp : z_ssp_t := idle; begin if rising_edge(tb_i_clk) then case z_ssp is when idle => if tb_o_send = '1' then v_cnt := 0; tb_i_sent <= '1'; z_ssp := busy; end if; when busy => if v_cnt = 10 then v_cnt := 0; tb_i_sent <= '0'; z_ssp := sending; else v_cnt := v_cnt + 1; end if; when sending => if v_cnt = 20 then v_cnt := 0; tb_i_sent <= '1'; z_ssp := idle; else v_cnt := v_cnt + 1; end if; end case; end if; end process p_ssp; end;