Added a MSB first option to the transmitter.

uart_tx.gtkw

@@ -1,18 +1,18 @@
 [*]
 [*] GTKWave Analyzer v3.3.98 (w)1999-2019 BSI
-[*] Mon Jul  6 17:13:37 2020
+[*] Sun Nov  1 16:28:41 2020
 [*]
-[dumpfile] "/home/maximilian/vga_uart_grabber_vhdl/uart_tx.vcd"
-[dumpfile_mtime] "Mon Jul  6 17:13:29 2020"
-[dumpfile_size] 4538783
-[savefile] "/home/maximilian/vga_uart_grabber_vhdl/uart_tx.gtkw"
+[dumpfile] "/home/maximilian/vga_uart_grabber_vhdl/uart_vhdl/uart_tx.vcd"
+[dumpfile_mtime] "Sun Nov  1 16:28:29 2020"
+[dumpfile_size] 2910
+[savefile] "/home/maximilian/vga_uart_grabber_vhdl/uart_vhdl/uart_tx.gtkw"
 [timestart] 0
-[size] 1920 1051
+[size] 1366 703
 [pos] 3 0
-*-33.258671 3810000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-30.258671 3810000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] uart_tx_tb.
 [sst_width] 212
-[signals_width] 182
+[signals_width] 353
 [sst_expanded] 1
 [sst_vpaned_height] 300
 @28

uart_tx.vhd

@@ -7,6 +7,7 @@ entity uart_tx is
         i_clk_baudrate  : in  std_logic;
         i_reset_n       : in  std_logic;
         i_tx_send       : in  std_logic;
+        i_msb_first     : in  std_logic;
         i_tx_data_vec   : in  std_logic_vector(7 downto 0);
         o_tx_pin        : out std_logic;
         o_tx_sent       : out std_logic
@@ -18,6 +19,18 @@ architecture uart_tx_rtl of uart_tx is
   constant  c_START_BIT   : std_logic := '0';
   constant  c_STOP_BIT    : std_logic := '1';
   signal    s_tx_buf_vec  : std_logic_vector(7 downto 0) := x"00";
+
+  function reverse_any_vector (a: in std_logic_vector)
+  return std_logic_vector is
+    variable result: std_logic_vector(a'RANGE);
+    alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
+  begin
+    for i in aa'RANGE loop
+      result(i) := aa(i);
+    end loop;
+    return result;
+  end; -- function reverse_any_vector
+
 begin
   uart_tx_main_proc: process(i_clk_baudrate)
     variable z_uart : z_uart_t := idle;
@@ -33,7 +46,11 @@ begin
         case z_uart is
           when idle =>
             if (i_tx_send = '1') then
-              s_tx_buf_vec <= i_tx_data_vec;
+              if (i_msb_first = '1') then
+                s_tx_buf_vec <= i_tx_data_vec;
+              else
+                s_tx_buf_vec <= reverse_any_vector(i_tx_data_vec);
+              end if;
               o_tx_sent <= '0';
               o_tx_pin <= c_START_BIT;
               z_uart := sending;

uart_tx_tb.vhd

@@ -15,6 +15,7 @@ architecture uart_tx_tb_rtl of uart_tx_tb is
           i_clk_baudrate  : in  std_logic;
           i_reset_n       : in  std_logic;
           i_tx_send       : in  std_logic;
+          i_msb_first     : in  std_logic;
           i_tx_data_vec   : in  std_logic_vector(7 downto 0);
           o_tx_pin        : out std_logic;
           o_tx_sent       : out std_logic
@@ -26,6 +27,7 @@ architecture uart_tx_tb_rtl of uart_tx_tb is
   signal tb_i_clk_baudrate  : std_logic := '0';
   signal tb_i_reset_n       : std_logic := '0';
   signal tb_i_tx_send       : std_logic := '0';
+  signal tb_i_msb_first     : std_logic := '0';
   signal tb_i_tx_data_vec   : std_logic_vector(7 downto 0) := x"00";
   signal tb_o_tx_pin        : std_logic := '0';
   signal tb_o_tx_sent       : std_logic := '0';
@@ -36,6 +38,7 @@ begin
                                 i_clk_baudrate  => tb_i_clk_baudrate,
                                 i_reset_n       => tb_i_reset_n,
                                 i_tx_send       => tb_i_tx_send,
+                                i_msb_first     => tb_i_msb_first,
                                 i_tx_data_vec   => tb_i_tx_data_vec,
                                 o_tx_pin        => tb_o_tx_pin,
                                 o_tx_sent       => tb_o_tx_sent
@@ -64,6 +67,7 @@ begin
     for sanny in nice_words'range loop
       -- Feed with data and tell transmitter to send.
       tb_i_tx_data_vec <= nice_words(sanny);
+      tb_i_msb_first <= not tb_i_msb_first;
       tb_i_tx_send <= '1';
       -- Wait until transmitted then finish simulation.
       wait until tb_o_tx_sent = '1';