Quick fix concerning bit order

string_sender.vhdl

@@ -32,6 +32,17 @@ architecture string_sender_rtl of string_sender is
     return v_ret;
   end function f_char_to_vector;
 
+  function reverse_any_vector (a: in std_logic_vector)
+  return std_logic_vector is
+    variable result: std_logic_vector(a'RANGE);
+    alias aa: std_logic_vector(a'REVERSE_RANGE) is a;
+  begin
+    for i in aa'RANGE loop
+      result(i) := aa(i);
+    end loop;
+    return result;
+  end; -- function reverse_any_vector
+
 begin
   string_sender_main_proc: process(i_clk)
     constant c_msg : string(1 to 13) := "Hello World!" & LF;
@@ -55,7 +66,7 @@ begin
              end if;
           when init_transmission =>
              if i_sent = '1' then
-                o_char <= f_char_to_vector(c_msg(v_ind));
+                o_char <= reverse_any_vector(f_char_to_vector(c_msg(v_ind)));
                 o_send <= '1';
                 z_sender := wait_for_transmission_start;
               end if;