Maximilian Stiefel
4 years ago
7 changed files with 176 additions and 24 deletions
@ -1,27 +1,29 @@ |
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[*] |
[*] |
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[*] GTKWave Analyzer v3.3.98 (w)1999-2019 BSI |
[*] GTKWave Analyzer v3.3.98 (w)1999-2019 BSI |
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[*] Sat Jul 11 11:53:05 2020 |
[*] Sat Jul 11 17:55:22 2020 |
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[*] |
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[dumpfile] "/home/maximilian/vga_uart_grabber_vhdl/string_sender.vcd" |
[dumpfile] "/home/maximilian/vga_uart_grabber_vhdl/string_sender.vcd" |
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[dumpfile_mtime] "Sat Jul 11 11:50:19 2020" |
[dumpfile_mtime] "Sat Jul 11 17:52:42 2020" |
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[dumpfile_size] 410742 |
[dumpfile_size] 404232 |
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[savefile] "/home/maximilian/vga_uart_grabber_vhdl/string_sender.gtkw" |
[savefile] "/home/maximilian/vga_uart_grabber_vhdl/string_sender.gtkw" |
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[timestart] 0 |
[timestart] 0 |
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[size] 1366 703 |
[size] 1366 703 |
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[pos] -1 -1 |
[pos] 3 0 |
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*-30.103638 200000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 |
*-35.103638 692000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 |
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[treeopen] string_sender_tb. |
[treeopen] string_sender_tb. |
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[sst_width] 212 |
[sst_width] 212 |
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[signals_width] 299 |
[signals_width] 299 |
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[sst_expanded] 1 |
[sst_expanded] 1 |
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[sst_vpaned_height] 179 |
[sst_vpaned_height] 300 |
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@28 |
@28 |
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string_sender_tb.tb_i_clk |
string_sender_tb.tb_i_clk |
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string_sender_tb.tb_i_reset_n |
string_sender_tb.tb_i_reset_n |
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string_sender_tb.tb_o_send |
string_sender_tb.tb_o_send |
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@22 |
@22 |
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string_sender_tb.tb_o_char[7:0] |
string_sender_tb.tb_o_char[7:0] |
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@29 |
@28 |
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string_sender_tb.tb_i_sent |
string_sender_tb.tb_i_sent |
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@29 |
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string_sender_tb.tb_done |
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[pattern_trace] 1 |
[pattern_trace] 1 |
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[pattern_trace] 0 |
[pattern_trace] 0 |
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@ -0,0 +1,26 @@ |
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[*] |
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[*] GTKWave Analyzer v3.3.98 (w)1999-2019 BSI |
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[*] Sat Jul 11 19:58:56 2020 |
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[*] |
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[dumpfile] "/home/maximilian/vga_uart_grabber_vhdl/top.vcd" |
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[dumpfile_mtime] "Sat Jul 11 19:57:41 2020" |
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[dumpfile_size] 844762900 |
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[savefile] "/home/maximilian/vga_uart_grabber_vhdl/top.gtkw" |
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[timestart] 0 |
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[size] 1920 1051 |
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[pos] -1 -1 |
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*-47.083782 364693745000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 |
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[treeopen] top_tb. |
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[treeopen] top_tb.top_0. |
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[sst_width] 212 |
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[signals_width] 179 |
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[sst_expanded] 1 |
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[sst_vpaned_height] 300 |
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@28 |
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top_tb.tb_clk_12mhz |
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top_tb.tb_done |
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top_tb.tb_led |
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@29 |
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top_tb.top_0.clock_divider_1.o_clk |
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[pattern_trace] 1 |
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[pattern_trace] 0 |
@ -0,0 +1,70 @@ |
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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.numeric_std.all; |
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entity top is |
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port ( |
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i_clk_12mhz : in std_logic; |
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i_reset_n : in std_logic; |
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o_tx_pin : out std_logic; |
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o_led : out std_logic |
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); |
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end top; |
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architecture top_rtl of top is |
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constant c_N_0 : integer := 30; |
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constant c_divisor_0 : integer := 12e6; |
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constant c_divisor_1 : integer := 1250; |
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constant s_divisor_vec_0 : std_logic_vector(c_N_0-1 downto 0) |
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:= std_logic_vector(to_unsigned(c_divisor_0, c_N_0)); |
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constant s_divisor_vec_1 : std_logic_vector(c_N_0-1 downto 0) |
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:= std_logic_vector(to_unsigned(c_divisor_1, c_N_0)); |
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signal s_send_clk : std_logic := '0'; |
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signal s_sent : std_logic := '1'; |
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signal s_send : std_logic := '0'; |
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signal s_char_vec : std_logic_vector(7 downto 0) := (others => '0'); |
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signal s_baudrate_clk : std_logic := '0'; |
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begin |
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-- Clock divider 0 gives the signal for when to send the string |
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clock_divider_0: entity work.clock_divider(clock_divider_rtl) |
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generic map (N => c_N_0) |
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port map ( |
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i_clk => i_clk_12mhz, |
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i_reset_n => i_reset_n, |
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i_divisor_vec => s_divisor_vec_0, |
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o_clk => s_send_clk |
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); |
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-- Clock divider 1 produces a baudrate of 9600 Bd |
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clock_divider_1: entity work.clock_divider(clock_divider_rtl) |
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generic map (N => c_N_0) |
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port map ( |
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i_clk => i_clk_12mhz, |
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i_reset_n => i_reset_n, |
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i_divisor_vec => s_divisor_vec_1, |
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o_clk => s_baudrate_clk |
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); |
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-- String sender component |
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string_send_0: entity work.string_sender(string_sender_rtl) |
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port map ( |
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i_clk => i_clk_12mhz, |
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i_send_clk => s_send_clk, |
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i_sent => s_sent, |
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i_reset_n => i_reset_n, |
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o_send => s_send, |
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o_char => s_char_vec |
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); |
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-- UART transmitter component |
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uart_tx_0: entity work.uart_tx(uart_tx_rtl) |
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port map ( |
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i_clk_baudrate => s_baudrate_clk, |
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i_reset_n => i_reset_n, |
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i_tx_send => s_send, |
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i_tx_data_vec => s_char_vec, |
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o_tx_pin => o_tx_pin, |
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o_tx_sent => s_sent |
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); |
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-- Couple send signal with LED |
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o_led <= s_send; |
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end; |
@ -0,0 +1,48 @@ |
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library ieee; |
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use ieee.std_logic_1164.all; |
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use ieee.numeric_std.all; |
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entity top_tb is |
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end top_tb; |
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architecture top_tb_rtl of top_tb is |
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constant c_CLK_PERIOD : time := 83.33 ns; |
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signal tb_clk_12mhz : std_logic := '0'; |
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signal tb_reset_n : std_logic := '1'; |
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signal tb_tx_pin : std_logic := '1'; |
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signal tb_led : std_logic := '0'; |
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signal tb_done : std_logic := '0'; |
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begin |
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top_0: entity work.top(top_rtl) |
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port map( |
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i_clk_12mhz => tb_clk_12mhz, |
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i_reset_n => tb_reset_n, |
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o_tx_pin => tb_tx_pin, |
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o_led => tb_led |
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); |
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-- Generate clock. |
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p_clock : process is |
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begin |
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if (tb_done = '0') then |
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tb_clk_12mhz <= '0'; |
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wait for c_CLK_PERIOD/2; |
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tb_clk_12mhz <= '1'; |
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wait for c_CLK_PERIOD/2; |
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elsif tb_done = '1' then |
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wait; |
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end if; |
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end process p_clock; |
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-- Process for stimuli. |
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p_stimuli : process is |
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begin |
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tb_reset_n <= '0'; |
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wait for 2*c_CLK_PERIOD; |
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tb_reset_n <= '1'; |
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wait for 1100 ms; |
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tb_done <= '1'; |
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assert false report "end of test" severity note; |
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wait; |
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end process p_stimuli; |
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end; |
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