Added .pcf file

top.vhdl

@@ -7,6 +7,9 @@ entity top is
         i_clk_12mhz : in std_logic;
         i_reset_n   : in std_logic;
         o_tx_pin    : out std_logic;
+        o_dcd_n     : out std_logic;
+        o_dsr_n     : out std_logic;
+        o_cts_n     : out std_logic;
         o_led       : out std_logic
        );
 end top;

uart_tx.pcf

@@ -0,0 +1,7 @@
+set_io i_clk_12mhz 21
+set_io i_reset_n 78
+set_io o_tx_pin 8
+set_io o_dcd_n 1
+set_io o_dsr_n 2
+set_io o_cts_n 4
+set_io o_led 99