Added a .lpf file for the ECP5 eval. board

top.vhd

@@ -7,9 +7,9 @@ entity top is
         i_clk_12mhz : in std_logic;
         i_reset_n   : in std_logic;
         o_tx_pin    : out std_logic;
-        o_dcd_n     : out std_logic;
+--        o_dcd_n     : out std_logic;
-        o_dsr_n     : out std_logic;
+--        o_dsr_n     : out std_logic;
-        o_cts_n     : out std_logic;
+--        o_cts_n     : out std_logic;
         o_led       : out std_logic
        );
 end top;
@@ -25,7 +25,7 @@ architecture top_rtl of top is
 
   signal s_send_clk       : std_logic := '0';
   signal s_sent           : std_logic := '1';
-  signal s_send           : std_logic := '0';
+  signal s_send           : std_logic := '1';
   signal s_char_vec       : std_logic_vector(7 downto 0) := (others => '0');
   signal s_baudrate_clk   : std_logic := '0';
 
@@ -69,5 +69,5 @@ begin
               o_tx_sent       => s_sent
             );
   -- Couple send signal with LED
-  o_led <= s_send;
+  o_led <= not s_send;
 end;

top_ecp5_eval.lpf

@@ -0,0 +1,11 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+LOCATE COMP "i_clk_12mhz" SITE "A10" ;
+LOCATE COMP "i_reset_n" SITE "P4" ;
+LOCATE COMP "o_tx_pin" SITE "C6" ;
+LOCATE COMP "o_led" SITE "A13" ;
+IOBUF PORT "i_reset_n" IO_TYPE=LVCMOS33 ;
+IOBUF PORT "i_clk_12mhz" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_tx_pin" PULLMODE=NONE IO_TYPE=LVCMOS33 ;
+IOBUF PORT "o_led" IO_TYPE=LVCMOS25 OPENDRAIN=OFF ;
+FREQUENCY PORT "i_clk_12mhz" 12.000000 MHz ;