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55 lines
1.6 KiB
55 lines
1.6 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity uart_tx is
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port(
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i_clk_baudrate : in std_logic;
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i_reset_n : in std_logic;
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i_tx_send : in std_logic;
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i_tx_data_vec : in std_logic_vector(7 downto 0);
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o_tx_pin : out std_logic;
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o_tx_sent : out std_logic
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);
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end;
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architecture uart_tx_rtl of uart_tx is
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type z_uart_t is (idle, sending);
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constant c_START_BIT : std_logic := '0';
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constant c_STOP_BIT : std_logic := '1';
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signal s_tx_buf_vec : std_logic_vector(7 downto 0) := x"00";
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begin
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uart_tx_main_proc: process(i_clk_baudrate)
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variable z_uart : z_uart_t := idle;
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variable v_trans_cnt : integer range 0 to 10 := 0;
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begin
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if rising_edge(i_clk_baudrate) then
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-- Syncrhonous reset only.
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if (i_reset_n = '0') then
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o_tx_pin <= '1';
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o_tx_sent <= '1';
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z_uart := idle;
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else
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case z_uart is
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when idle =>
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if (i_tx_send = '1') then
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s_tx_buf_vec <= i_tx_data_vec;
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o_tx_sent <= '0';
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o_tx_pin <= c_START_BIT;
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z_uart := sending;
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end if;
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when sending =>
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if (v_trans_cnt >= 8) then
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v_trans_cnt := 0;
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o_tx_sent <= '1';
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o_tx_pin <= c_STOP_BIT;
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z_uart := idle;
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else
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o_tx_pin <= s_tx_buf_vec(7-v_trans_cnt);
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v_trans_cnt := v_trans_cnt + 1;
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end if;
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end case;
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end if; -- reset
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end if; -- clk
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end process uart_tx_main_proc; -- main
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end;
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