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52 lines
1.5 KiB
52 lines
1.5 KiB
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity clock_divider_tb is
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end clock_divider_tb;
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architecture clock_divider_tb_rtl of clock_divider_tb is
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-- 10 MHz clock
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constant c_CLK_PERIOD : time := 100 ns;
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constant c_N : integer := 8;
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--for clock_divider_0: clock_divider use entity work.clock_divider;
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signal tb_i_clk : std_logic := '0';
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signal tb_i_reset_n : std_logic := '1';
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signal tb_i_divisor_vec : std_logic_vector(c_N-1 downto 0) := x"00";
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signal tb_o_clk : std_logic := '0';
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signal tb_done : std_logic := '0';
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begin
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--clock_divider_0: clock_divider
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clock_divider_0: entity work.clock_divider(clock_divider_rtl)
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generic map (N => c_N)
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port map (
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i_clk => tb_i_clk,
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i_reset_n => tb_i_reset_n,
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i_divisor_vec => tb_i_divisor_vec,
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o_clk => tb_o_clk
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);
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-- Generate clock.
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p_clock : process is
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begin
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if (tb_done = '0') then
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tb_i_clk <= '0';
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wait for c_CLK_PERIOD/2;
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tb_i_clk <= '1';
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wait for c_CLK_PERIOD/2;
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elsif tb_done = '1' then
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wait;
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end if;
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end process p_clock;
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-- Process for stimuli.
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p_stimuli : process is
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begin
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tb_i_divisor_vec <= x"02";
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tb_i_reset_n <= '0';
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wait for c_CLK_PERIOD;
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tb_i_reset_n <= '1';
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wait for 1 ms;
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tb_done <= '1';
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assert false report "end of test" severity note;
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wait;
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end process p_stimuli;
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end clock_divider_tb_rtl;
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