max_uart_vhdl/clock_divider_tb.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clock_divider_tb is
end clock_divider_tb;

architecture clock_divider_tb_rtl of clock_divider_tb is
  -- 10 MHz clock
  constant c_CLK_PERIOD : time := 100 ns;
  constant c_N : integer := 8;
  --for clock_divider_0: clock_divider use entity work.clock_divider;
  signal tb_i_clk         : std_logic := '0';
  signal tb_i_reset_n     : std_logic := '1';
  signal tb_i_divisor_vec : std_logic_vector(c_N-1 downto 0) := x"00";
  signal tb_o_clk         : std_logic := '0';
  signal tb_done          : std_logic := '0';
begin
  --clock_divider_0: clock_divider
  clock_divider_0: entity work.clock_divider(clock_divider_rtl)
  generic map (N => c_N)
  port map (
             i_clk => tb_i_clk,
             i_reset_n => tb_i_reset_n,
             i_divisor_vec => tb_i_divisor_vec,
             o_clk => tb_o_clk
           );
  -- Generate clock.
  p_clock : process is
  begin
    if (tb_done = '0') then
      tb_i_clk <= '0';
      wait for c_CLK_PERIOD/2;
      tb_i_clk <= '1';
      wait for c_CLK_PERIOD/2;
    elsif tb_done = '1' then
      wait;
    end if;
  end process p_clock;
  -- Process for stimuli.
  p_stimuli : process is
  begin
    tb_i_divisor_vec <= x"02";
    tb_i_reset_n <= '0';
    wait for c_CLK_PERIOD;
    tb_i_reset_n <= '1';
    wait for 1 ms;
    tb_done <= '1';
    assert false report "end of test" severity note;
    wait;
  end process p_stimuli;
end clock_divider_tb_rtl;