max_uart_vhdl/clock_divider.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity clock_divider is
  generic (
            N : integer := 8
          );
  port    (
            i_clk         : in std_logic;
            i_reset_n     : in std_logic;
            i_divisor_vec : in std_logic_vector(N-1 downto 0);
            o_clk         : out std_logic
          );
end;

architecture clock_divider_rtl of clock_divider is
begin
  clock_divider_main_proc: process(i_clk)
    variable v_cnt      : integer range 0 to 2**N := 1;
    variable v_cnt_max  : integer range 0 to 2**N := 1;
    variable v_clk      : std_logic               := '0';
  begin
    if rising_edge(i_clk) then
      if (i_reset_n = '0') then
        v_cnt := 1;
        v_cnt_max := to_integer(unsigned(i_divisor_vec))/2;
        v_clk := '1';
      else
        if (v_cnt >= v_cnt_max) then
          v_cnt := 1;
          v_clk := not v_clk;
        else
          v_cnt := v_cnt + 1;
        end if;
      end if;
    end if;
    o_clk <= v_clk;
  end process clock_divider_main_proc;
end;