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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity clock_divider is
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generic (
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N : integer := 8
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);
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port (
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i_clk : in std_logic;
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i_reset_n : in std_logic;
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i_divisor_vec : in std_logic_vector(N-1 downto 0);
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o_clk : out std_logic
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);
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end;
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architecture clock_divider_rtl of clock_divider is
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begin
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clock_divider_main_proc: process(i_clk)
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variable v_cnt : integer range 0 to 2**N := 1;
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variable v_cnt_max : integer range 0 to 2**N := 1;
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variable v_clk : std_logic := '0';
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begin
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if rising_edge(i_clk) then
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if (i_reset_n = '0') then
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v_cnt := 1;
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v_cnt_max := to_integer(unsigned(i_divisor_vec))/2;
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v_clk := '1';
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else
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if (v_cnt >= v_cnt_max) then
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v_cnt := 1;
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v_clk := not v_clk;
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else
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v_cnt := v_cnt + 1;
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end if;
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end if;
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end if;
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o_clk <= v_clk;
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end process clock_divider_main_proc;
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end;
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