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133 lines
3.0 KiB
133 lines
3.0 KiB
7 years ago
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* ADA4522-4 SPICE Macro-model
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* Description: Amplifier
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* Generic Desc: HV, ZD, Low Noise, Non-RRin, RRout
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* Developed by: JG ADGT / VW ADSJ
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* Revision History:
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* 05/18/2015 - initial release for dual
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* 10/27/2015 - initial release for quad
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* 0.0 (05/2015)
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* Copyright 2015 by Analog Devices
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* T=25�C
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*
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* Refer to "README.DOC" file for License Statement. Use of this
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* model indicates your acceptance of the terms and provisions in
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* the License Statement.
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*
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* Node Assignments
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* noninverting input
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* | inverting input
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* | | positive supply
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* | | | negative supply
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* | | | | output
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* | | | | |
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* | | | | |
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.SUBCKT ADA4522 1 2 99 50 45
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*#ASSOC Category=Op-amp symbol=opamp
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*
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* INPUT STAGE
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*
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M1 4 7 8 8 PIX L=1E-6 W=1.18E-04
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M2 6 2 8 8 PIX L=1E-6 W=1.18E-04
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M3 14 7 18 18 NIX L=1E-6 W=1.18E-04
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M4 16 2 18 18 NIX L=1E-6 W=1.18E-04
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RD1 4 50 1.33E+04
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RD2 6 50 1.33E+04
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RD3 99 14 1.33E+04
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RD4 99 16 1.33E+04
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C1 4 6 6.7E-13
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C2 14 16 6.7E-13
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I1 99 8 3.00E-05
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I2 18 50 3.00E-05
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V1 99 9 2.113E+00
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V2 19 50 1.203E-01
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D1 8 9 DX
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D2 19 18 DX
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EOS 7 1 POLY(4) (73,98) (22,98) (81,98) (83,98) -9.1E-06 0.1 0.1 0.1 0.1
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IOS 1 2 100E-12
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V5 99 3 2.2
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D5 1 3 DX
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D6 50 1 DX
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V6 99 100 2.2
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D7 2 100 DX
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D8 50 2 DX
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Ccm1 1 50 35E-12
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Ccm2 2 50 35E-12
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Cdm 1 2 7.0E-12
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*
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*CMRR
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*
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E1 72 98 POLY(2) (1,98) (2,98) 0 5.25E-03 5.25E-03
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R10 72 73 1.89E+02
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R20 73 98 4.8E-01
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C10 72 73 1.00E-06
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*
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* PSRR
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*
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EPSY 21 98 POLY(1) (99,50) -2.712E-00 2.4
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RPS1 21 22 1.59E+05
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RPS2 22 98 3.18E-01
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CPS1 21 22 1.00E-06
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*
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*
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* VOLTAGE NOISE REFERENCE
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*
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VN1 80 98 0
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RN1 80 98 265E-05
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HN 81 98 VN1 6.6E0
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RNHH1 81 183 5.3
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CHH1 183 98 1E-012
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*
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*BPF
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*
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EV5 83 98 VALUE = { V(203,98)+V(205,98) }
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R94 204 98 300
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L92 200 210 6.0e-006
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C92 210 204 9e-011
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R93 200 204 5.5E03
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EV4 205 98 204 98 10.5
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EV3 203 98 202 98 5.5
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R92 202 98 200
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L91 200 201 3.0e-005
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C91 201 202 10e-010
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R91 200 202 1E03
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EV1 200 98 81 98 1
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*
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* INTERNAL VOLTAGE REFERENCE
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*
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EREF 98 0 POLY(2) (99,0) (50,0) 0 0.5 0.5
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GSY 99 50 POLY(1) (99,50) 805.1E-06 -1.55E-9
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*
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* GAIN STAGE
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*
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G1 98 30 POLY(2) (4,6) (14,16) 0 7.103E-03 7.103E-03
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R1 30 98 1.00E+06
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RZ 455 31 0.195E+00
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CF 30 31 4.05E-9
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EZ 455 98 (45,98) 1
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V3 32 30 -7.5E-04
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V4 30 33 -4.9E-04
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D3 32 98 DX
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D4 98 33 DX
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*
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* OUTPUT STAGE
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*
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M5 45 46 99 99 POX L=3E-6 W=20E-04
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M6 45 47 50 50 NOX L=3E-6 W=40E-04
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EG1 99 46 POLY(1) (98,30) 8.523E-01 1
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EG2 47 50 POLY(1) (30,98) 8.523E-01 1
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*EG1 99 46 POLY(1) (98,30) 8.523E-01 1
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*EG2 47 50 POLY(1) (30,98) 8.523E-01 1
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*
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* MODELS
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*
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.MODEL POX PMOS (LEVEL=2,KP=4.00E-05,VTO=-0.83,LAMBDA=0.047,RD=7)
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.MODEL NOX NMOS (LEVEL=2,KP=4.00E-05,VTO=+0.83,LAMBDA=0.047,RD=38)
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.MODEL PIX PMOS (LEVEL=2,KP=1.50E-05,VTO=-0.5,LAMBDA=0.047)
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.MODEL NIX NMOS (LEVEL=2,KP=4.00E-05,VTO=0.5,LAMBDA=0.022)
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.MODEL DX D(IS=1E-14,RS=0.1)
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*
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*
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.ENDS ADA4522
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*
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*$
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