Altium

Design Rule Verification Report

Date: 21-Aug-17
Time: 11:16:58 AM
Elapsed Time: 00:00:02
Filename: C:\Users\Elmar\Desktop\UU\UppSense\pcbs\digital_board_rev_2\uppsense.PcbDoc
Warnings: 0
Rule Violations: 0

Summary

Warnings Count
Total 0

Rule Violations Count
Clearance Constraint (Gap=0.2mm) (InPolygon),(All) 0
Clearance Constraint (Gap=0.2mm) (IsTrack AND AsMM(Width) > 0.2),(All) 0
Clearance Constraint (Gap=0.15mm) (All),(All) 0
Clearance Constraint (Gap=1.1mm) (HasFootprint('FEDUCIAL')),(All) 0
Clearance Constraint (Gap=0.25mm) (OnLayer('Keep-Out Layer')),(InPolygon) 0
Clearance Constraint (Gap=0.25mm) (OnLayer('Keep-Out Layer')),(All) 0
Short-Circuit Constraint (Allowed=No) (All),(All) 0
Un-Routed Net Constraint ( (All) ) 0
Modified Polygon (Allow modified: No), (Allow shelved: No) 0
Width Constraint (Min=0.15mm) (Max=100mm) (Preferred=0.2mm) (All) 0
Power Plane Connect Rule(Relief Connect )(Expansion=0.508mm) (Conductor Width=0.254mm) (Air Gap=0.254mm) (Entries=4) (All) 0
Hole Size Constraint (Min=0.025mm) (Max=20mm) (All) 0
Hole To Hole Clearance (Gap=0.254mm) (All),(All) 0
Minimum Solder Mask Sliver (Gap=0mm) (All),(All) 0
Silk To Solder Mask (Clearance=0mm) (IsPad),(All) 0
Silk to Silk (Clearance=0mm) (All),(All) 0
Net Antennae (Tolerance=0mm) (All) 0
Height Constraint (Min=0mm) (Max=1000mm) (Prefered=12.7mm) (All) 0
Total 0