From 8cd2783f4a7d59623e24e9eee4b4368065a450c5 Mon Sep 17 00:00:00 2001 From: elamre Date: Thu, 13 Apr 2017 19:05:50 +0200 Subject: [PATCH 1/4] proper --- ltspice/current source/ad8276.cir | 162 +++++++++++++++++++ ltspice/current source/current_source.op.raw | Bin 0 -> 2300 bytes 2 files changed, 162 insertions(+) create mode 100644 ltspice/current source/ad8276.cir create mode 100644 ltspice/current source/current_source.op.raw diff --git a/ltspice/current source/ad8276.cir b/ltspice/current source/ad8276.cir new file mode 100644 index 0000000..abc2a9d --- /dev/null +++ b/ltspice/current source/ad8276.cir @@ -0,0 +1,162 @@ +* AD8276 SPICE Macro-model +* Description: Amplifier +* Generic Desc: iPolar, DiffAmp, Low Cost,low power, G=1 +* Developed by: +* Revision History: 08/10/2012 - Updated to new header style +* 1.0 (12/2009) +* Copyright 2012 by Analog Devices, Inc. +* +* Refer to http://www.analog.com/Analog_Root/static/techSupport/designTools/spiceModels/license/spice_general.html for License Statement. Use of this model +* indicates your acceptance of the terms and provisions in the License Statement. +* +* BEGIN Notes: +* +* Not Modeled: +* +* Parameters modeled include: +* END Notes +* +* Node assignments + +IN -IN Vcc Vee Out Ref Sense +*$ +.subckt AD8276 Pin Nin Vcc Vee out Ref Sense +*** Internal Resistors +R63 Pin 1 Rideal 4.00E+04 +R62 Nin 2 Rideal 4.00E+04 +R61 Ref 1 Rideal 4.00E+04 +R65 Sense 2 Rideal 4.00E+04 +***Differential Stage +Q1 13 12 14 npn +Q2 17 2 16 npn +Rc1 98 13 Rideal 4.200E+00 +Rc2 98 17 Rideal 4.200E+00 +Re1 14 15 Rideal 4.148E+00 +Re2 15 16 Rideal 4.148E+00 +Ibias 15 51 1.00E+00 +Dcmlim1 18 15 DQUIET +Vcmlim1 18 51 -0.074 +***Voltage Noise Generation +HVnoise 9 7 Vvnoise 1 +VVnoise 501 0 0 +DVnoise 501 0 Dvnoise +RVnoise 501 0 3.37959E-06 +***Current Noise Generation on +IN +FInoise1 12 0 VInoise1 1 +VInoise1 502 0 0 +DInoise1 502 0 DInoise1 +RInoise1 502 0 287500 +***Current Noise Generation on -IN +FInoise2 2 0 VInoise2 1 +VInoise2 503 0 0 +DInoise2 503 0 DInoise2 +RInoise2 503 0 287500 +***Common Mode Injection +Rcm1 1 601 Rideal 100Meg +Rcm2 2 601 Rideal 100Meg +Gcmr 0 602 601 75 1.00E-06 +Rcmr1 602 603 Rideal 1Meg +Rcmr2 603 604 Rideal 3.162E+01 +Lcmr 604 0 1.007E-03 +Ecmr 10 9 603 0 1.000E+00 +***Positive Power Supply Rejection +Epsr1 700 0 98 0 1 +Rpsr1 700 701 Rideal 1.00E+02 +Rpsr2 701 702 Rideal 1.000E-03 +Lpsr1 702 0 3.979E-06 +Epsr2 11 10 701 0 1 +***Negative Power Supply Rejection +Epsr3 703 0 51 0 1 +Rpsr3 703 704 Rideal 1.00E+02 +Rpsr4 704 705 Rideal 1.000E-03 +Lpsr2 705 0 5.305E-07 +Epsr4 12 11 704 0 1 +***Input Offset and Bias +Vos 1 7 1.000E-04 +Ios 1 2 0.000E+00 +***Input Impedance +Cinv 2 0 6.00E-13 +Cninv 1 0 6.00E-13 +***1st Gain and Slew limiting +Gslew 0 101 17 13 1.0000E+00 +Rslew 101 0 Rideal 2.50E+02 +Dslew1 101 102 DZENER +Dslew2 0 102 DZENER +***Second Gain and Dominant Pole with Output Voltage Limiting +Gp1 51 201 101 0 4.173E-08 +Rp1 201 51 Rideal 3.032E+13 +Cp1 201 51 1.50E-12 +Vlim1 97 206 0.35 +Dlim1 201 206 dquiet +Vlim2 207 52 0.35 +Dlim2 207 201 dquiet +Esupref1 97 98 51 0 1 +Esupref2 52 51 51 0 1 +***Second Pole +Gp2 0 202 201 51 1.00E-03 +Rp2 202 0 Rideal 1.00E+03 +Cp2 202 0 3.1831E-11 +***Third Pole +Gp3 0 203 202 0 1.00E-03 +Rp3 203 0 Rideal 1.00E+03 +Cp3 203 0 3.1831E-11 +***Fourth Pole +Gp4 0 204 203 0 1.00E-03 +Rp4 204 0 Rideal 1.00E+03 +Cp4 204 0 1.59155E-16 +***Fifth Pole +Gp5 0 205 204 0 1.00E-03 +Rp5 205 0 Rideal 1.00E+03 +Cp5 205 0 1.592E-16 +***First Zero +Gz1 0 301 205 0 1.00E-03 +Rz1 301 302 Rideal 1.00E+03 +Lz1 302 0 1.061E-04 +***Second Zero +Gz2 0 303 301 0 1.00E-03 +Rz2 303 304 Rideal 1.00E+03 +Lz2 304 0 1.592E-10 +***Third Zero +Gz3 0 305 303 0 1.00E-03 +Rz3 305 306 Rideal 1.00E+03 +Lz3 306 0 1.59E-10 +***Buffer +Gbuf 0 401 305 0 1.00E-04 +Rbuf 401 0 Rideal 1.00E+04 +***Output with current limiting +Eout 404 0 401 0 1.000E+00 +Rout 404 405 RIDEAL 1.000E+00 +Lout 405 406 1.00E-19 +Cout 406 0 5.70E-11 +Voutmon 406 4 0 +Dout1 401 407 Dquiet +Vout1 407 406 -6.150E-01 +Dout2 408 401 Dquiet +Vout2 406 408 -6.150E-01 +Rsmall 4 out 1000 +***Voltage reference generator +Eref1 98 0 Vcc 0 1 +Eref2 51 0 Vee 0 1 +Rref1 98 901 Rideal 100Meg +Rref2 901 51 Rideal 100Meg +Eref3 75 0 901 0 1 +***Supply current correction +Iq Vcc Vee 0.00020 +Fsup1 Vcc 0 Voutmon 1 +*DZsup1 0 802 DZENER2 +*Dsup1 Vcc 802 DQUIET +Fsup2 0 Vee Voutmon -1 +*DZsup2 804 0 DZENER2 +*Dsup2 804 Vee DQUIET +***models +.model Rideal res T_ABS=27 +.model Rnoise res T_ABS=27 +.model npn npn BF= 8333332.33333333 +.model dquiet d +.model dvnoise d KF=980000 +.model dinoise1 d KF=0.000576 +.model dinoise2 d KF=0.000576 +.model dzener d BV=38.9444143409777 +.model dzener2 d BV=50 +.ends + + diff --git a/ltspice/current source/current_source.op.raw b/ltspice/current source/current_source.op.raw new file mode 100644 index 0000000000000000000000000000000000000000..fcfb629dc0fdd765f0adbef015f27c6e84e0dace GIT binary patch literal 2300 zcmdUwL2nX46vy9{z4Q~9Y~rO_MRtLfYPGf+lTE6nm69fs5TIBaTOjO0?8WckkwX(d zfH$jY(jGKk{4Dw*^!H{^AhKaOn$6D6y!rp%oA>@Rvn4r_NRFi`cg2;PypQNrWKTkD zUD^uYV>yu;ql!Fc6v}HjZRr@?o@qObo-@}nyb6qnUI*_DtQFcG{H{SnL+du1OucRz|Dn6Muvm`LnYwh<_gs z#P~hf1tP`VA{y&1%*qYMee~AzttX=iH-+zUlox~YCs2M2 zDm#J7#h`K%sC*16KScHAb_`$880ExysLqy=G!Lu0#z>ln)%^|Y((|bQC{-n7R5!P2G z=IOZ{=jpjm7SZm5QAE8fk}>Um7%}yJna$iZ{|o&`ol+M^B6s2ZLH6Ui$oq%qZ;R`n zKRu=YMaN%xHwJ^j{TDx?wT18dh3nsXS3AL3VK+FtP#fd5<@B}7@;mpE@s-+t{k(IF M_XD Date: Thu, 13 Apr 2017 19:06:10 +0200 Subject: [PATCH 2/4] completed bom --- docs/bom/current.csv | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/bom/current.csv b/docs/bom/current.csv index d1e1e15..4fad60a 100644 --- a/docs/bom/current.csv +++ b/docs/bom/current.csv @@ -2,7 +2,10 @@ Farnell,, Article, Ordercode, Min. Quantity Differential Amp,1827398,1 Opamp,2305612,1 -100 Ohm, 2504961RL,5 +100 Ohm, 2504961RL,1 Opamp,9425845,1 mmbt3904,1773602,2 MCP1702T,1331491,1 +1k ohm,9237496,10 +5 ohm,1353228,1 +19k ohm,2303683,10 From 42257e893d68f78cd268c8582305a58c7a477a5c Mon Sep 17 00:00:00 2001 From: elamre Date: Thu, 13 Apr 2017 19:06:18 +0200 Subject: [PATCH 3/4] start with pcb --- pcbs/CurrentSource/CurrentSource.PrjPcb | 858 ++++++++++++++++++++++++ pcbs/CurrentSource/currentsource.SchDoc | Bin 0 -> 71168 bytes 2 files changed, 858 insertions(+) create mode 100644 pcbs/CurrentSource/CurrentSource.PrjPcb create mode 100644 pcbs/CurrentSource/currentsource.SchDoc diff --git a/pcbs/CurrentSource/CurrentSource.PrjPcb b/pcbs/CurrentSource/CurrentSource.PrjPcb new file mode 100644 index 0000000..c8be536 --- /dev/null +++ b/pcbs/CurrentSource/CurrentSource.PrjPcb @@ -0,0 +1,858 @@ +[Design] +Version=1.0 +HierarchyMode=0 +ChannelRoomNamingStyle=0 +ReleasesFolder= +ReleaseVaultGUID= +ReleaseVaultName= +ChannelDesignatorFormatString=$Component_$RoomName +ChannelRoomLevelSeperator=_ +OpenOutputs=1 +ArchiveProject=0 +TimestampOutput=0 +SeparateFolders=0 +TemplateLocationPath= +PinSwapBy_Netlabel=1 +PinSwapBy_Pin=1 +AllowPortNetNames=0 +AllowSheetEntryNetNames=1 +AppendSheetNumberToLocalNets=0 +NetlistSinglePinNets=0 +DefaultConfiguration=Default Configuration +UserID=0xFFFFFFFF +DefaultPcbProtel=1 +DefaultPcbPcad=0 +ReorderDocumentsOnCompile=1 +NameNetsHierarchically=0 +PowerPortNamesTakePriority=0 +PushECOToAnnotationFile=1 +DItemRevisionGUID= +ReportSuppressedErrorsInMessages=0 +FSMCodingStyle=eFMSDropDownList_OneProcess +FSMEncodingStyle=eFMSDropDownList_OneHot +OutputPath= +LogFolderPath= +ManagedProjectGUID= + +[Preferences] +PrefsVaultGUID= +PrefsRevisionGUID= + +[Configuration1] +Name=Default Configuration +ParameterCount=0 +ConstraintFileCount=0 +ReleaseItemId= +CurrentRevision= +Variant=[No Variations] +OutputJobsCount=0 + +[OutputGroup1] +Name=Netlist Outputs +Description= +TargetPrinter=Microsoft Print to PDF +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=PCADNetlist +OutputName1=PCAD Netlist +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +OutputType2=Verilog +OutputName2=Verilog File +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +OutputType3=VHDL +OutputName3=VHDL File +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 + +[OutputGroup2] +Name=Simulator Outputs +Description= +TargetPrinter=Microsoft Print to PDF +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 + +[OutputGroup3] +Name=Documentation Outputs +Description= +TargetPrinter=Microsoft Print to PDF +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Assembler Source Print +OutputName1=Assembler Source Prints +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1 +OutputType2=C Source Print +OutputName2=C Source Prints +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1 +OutputType3=C/C++ Header Print +OutputName3=C/C++ Header Prints +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1 +OutputType4=C++ Source Print +OutputName4=C++ Source Prints +OutputDocumentPath4= +OutputVariantName4= +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1 +OutputType5=Composite +OutputName5=Composite Drawing +OutputDocumentPath5= +OutputVariantName5= +OutputDefault5=0 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+PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Assembly +OutputName1=Assembly Drawings +OutputDocumentPath1= +OutputVariantName1=[No Variations] +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1 +OutputType2=Pick Place +OutputName2=Generates pick and place files +OutputDocumentPath2= +OutputVariantName2=[No Variations] +OutputDefault2=0 +OutputType3=Test Points For Assembly +OutputName3=Test Point Report +OutputDocumentPath3= +OutputVariantName3=[No Variations] +OutputDefault3=0 + +[OutputGroup5] +Name=Fabrication Outputs +Description= +TargetPrinter=Microsoft Print to PDF +PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintJobKind=1|PrintWhat=1 +OutputType1=Board Stack Report +OutputName1=Report Board Stack +OutputDocumentPath1= +OutputVariantName1= +OutputDefault1=0 +PageOptions1=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1 +OutputType2=CompositeDrill +OutputName2=Composite Drill Drawing +OutputDocumentPath2= +OutputVariantName2= +OutputDefault2=0 +PageOptions2=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1 +OutputType3=Drill +OutputName3=Drill Drawing/Guides +OutputDocumentPath3= +OutputVariantName3= +OutputDefault3=0 +PageOptions3=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1 +OutputType4=Final +OutputName4=Final Artwork Prints +OutputDocumentPath4= +OutputVariantName4=[No Variations] +OutputDefault4=0 +PageOptions4=Record=PageOptions|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-3|MediaType=1|DitherType=10|PrintScaleMode=1|PaperKind=Letter|PaperIndex=1 +OutputType5=Gerber +OutputName5=Gerber Files +OutputDocumentPath5= +OutputVariantName5=[No Variations] +OutputDefault5=0 +OutputType6=Gerber X2 +OutputName6=Gerber X2 Files +OutputDocumentPath6= +OutputVariantName6= +OutputDefault6=0 +OutputType7=IPC2581 +OutputName7=IPC-2581 Files +OutputDocumentPath7= +OutputVariantName7= +OutputDefault7=0 +OutputType8=Mask +OutputName8=Solder/Paste Mask Prints +OutputDocumentPath8= +OutputVariantName8= +OutputDefault8=0 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